Field of the Invention
This invention relates to content addressable memories. More specifically, the invention provides a magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM).
Brief Description of the Prior Art
Magnetic Tunnel Junction (MTJ) is a spintronic device which stores data in the form of spin of an electron, unlike a static Complementary Metal-Oxide-Semiconductor (CMOS) memory cell, which stores data in the form of electric potential. An MJT device consists of three layers—a layer of magnetic oxide sandwiched between two layers of magnetic material. Data is stored in the form of magnetization in the two magnetic material layers. A logic ‘0’ is stored when the two magnetic layers are magnetized in the same direction and a logic ‘1’ is stored when the two magnetic layers are magnetized in the opposite direction. FIG. 1A illustrates an MTJ device configuration in parallel and antiparallel states.
Pinned Layer (PL) magnetization exhibits a fixed magnetization, whereas Free Layer (FL) magnetization can be polarized parallel or anti-parallel with respect to the PL. In this context, it should be noted that the resistance of MTJ is high when PL and FL are in antiparallel configuration, whereas the resistance of MJT is low when PL an FL are parallel to each other. The value written to the MTJ depends on the direction and the strength of the charge current. The minimum current required to flip the state of the MTJ is called the critical current. FIG. 1B illustrates the directions charge current to write ‘1’ and ‘0’ to an MTJ device.
Tunnel Magneto Resistance (TMR) is the ratio of electrical resistances of the MTJ structure in parallel and antiparallel polarization states of FL relative to PL magnetization. If RH is the MTJ resistance in an antiparallel state and RL is the MTJ resistance in a parallel state, the TMR is defined as
  TMR  =                    R        H            -              R        L                    R      L      
Content Addressable Memory (CAM) is widely used in pattern matching, internet data processing, packet forwarding, for tag bits storage in a processor cache, for associative memory and in many other fields where searching a specific pattern of data is a major operation. The special functionality of the content search in CAM requires a comparison circuitry integrated with the memory cell. The required comparator, in addition to the memory element itself, adds area and power overhead in CAMs.
CAMs can be divided into two categories depending on the number of states that can be stored in the memory cell, namely: binary CAM (BCAM) and ternary CAM (TCAM). BCAM stores a binary bit, namely ‘0’ and ‘1’, whereas TCAM can store three possible values, namely ‘1’, ‘0’, and ‘don't care’ (X). CAMs can be further categorized into two topologies, namely NOR and NAND type (see FIGS. 1C-1D). The stored bits are compared with the data on the search line (SL) and its complement (\SL) by XOR operation with the transistor network M1, M2, M3, and M4. To store data in a TCAM cell having a NOR-type architecture, data bit and the complement are stored in two SRAM cells.
The ‘don't care’ bit can be realized by storing ‘1’ in both SRAM cells, i.e., D=\D=1. In the case of a match, both SL-D and \SL-\D paths are disconnected, and the match line remains precharged. In the case of miss, either of the SL-D or \SL-\D connect ML to ground, which discharges the precharged ML.
In a NAND-type architecture, TCAM cells are connected in series. Data bit D and \D are derived from a single SRAM cell, unlike two SRAM cells in a NOR-type TCAM. The stored bit is masked by using a mask bit (M) in a parallel SRAM cell.
In case of match, the precharged ML is connected to ground by series TCAM cells of the word by turning the NMOS transistor M1 ‘ON’. Storing the mask bit as ‘1’ enables transistor M2, despite match or miss, which implements ‘don't care’ functionality. CMOS TCAM uses two SRAM cells, thereby doubling the area overhead, compared to conventional SRAM cells.
However, conventional CAMs suffer from area, power, and speed limitations. As it pertains to TCAM, the need to store and match a ‘don't care’ matching state requires two storage bits, which further worsens the area overhead. CMOS CAM is power hungry due to power consumed in match line (ML), search line, and leakage of the bit cell. In nanometer technologies, leakage power constitutes a major portion of the total power consumed in CAM memory. Non-volatile technologies, which are more area efficient than status random-access memory (SRAM) and can provide zero leakage, are attractive in such a scenario. However, continued improvement of TCAM is needed.
Accordingly, what is needed is improved area efficiency and non-volatility using MTJ-based TCAM for on-chip CAM applications. However, in view of the art considered as a whole at the time the present invention was made, it was not obvious to those of ordinary skill in the field of this invention how the shortcomings of the prior art could be overcome.
While certain aspects of conventional technologies have been discussed to facilitate disclosure of the invention. Applicant in no way disclaims these technical aspects, and it is contemplated that the claimed invention may encompass one or more of the conventional technical aspects discussed herein.
The present invention may address one or more of the problems and deficiencies of the prior art discussed above. However, it is contemplated that the invention may prove useful in addressing other problems and deficiencies in a number of technical areas. Therefore, the claimed invention should not necessarily be construed as limited to addressing any of the particular problems or deficiencies discussed herein.
In this specification, where a document, act or item of knowledge is referred to or discussed, this reference or discussion is not an admission that the document, act or item of knowledge or any combination thereof was at the priority date, publicly available, known to the public, part of common general knowledge, or otherwise constitutes prior art under the applicable statutory provisions; or is known to be relevant to an attempt to solve any problem with which this specification is concerned.